Functional Description
Table 5-55. Data Values for Slave Read Registers (Sheet 2 of 2)
Register
Bits
Description
POWER_OK_BAD: Indicates the failure core power well ramp during
boot/resume. This bit will be active if the SLP_S3# pin is de-asserted
and PWROK pin is not asserted.
5
Thermal Trip: This bit will shadow the state of processor Thermal Trip
status bit (CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal
will not create a event message
6
7
Reserved: Default value is “X”
Note: Software should not expect a consistent value when this bit is
read through SMBUS/SMLINK
Contents of the Message 1 register. Refer to Section 13.9.8 for the
description of this register.
6
7
8
7:0
7:0
7:0
Contents of the Message 2 register. Refer to Section 13.9.8 for the
description of this register.
Contents of the TCO_WDCNT register. Refer to Section 13.9.9 for the
description of this register.
9
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Seconds of the RTC
Minutes of the RTC
Hours of the RTC
“Day of Week” of the RTC
“Day of Month” of the RTC
Month of the RTC
Year of the RTC
A
B
C
D
E
F
10h–FFh
Reserved
5.20.7.2.1
Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit –
Address– Write bit sequence. When the ICH10 detects that the address matches the
value in the Receive Slave Address register, it will assume that the protocol is always
followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In
other words, if a Start –Address–Read occurs (which is invalid for SMBus Read or Write
protocol), and the address matches the ICH10’s Slave Address, the ICH10 will still grab
the cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–
Read sequence beginning at bit 20. Once again, if the Address matches the ICH10’s
Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and
proceed with the Slave Read cycle.
Note:
An external microcontroller must not attempt to access the ICH10’s SMBus Slave logic
until at least 1 second after both RTCRST# and RSMRST# are deasserted (high).
5.20.7.3
Slave Read of RTC Time Bytes
The ICH10 SMBus slave interface allows external SMBus master to read the internal
RTC’s time byte registers.
The RTC time bytes are internally latched by the ICH10’s hardware whenever RTC time
is not changing and SMBus is idle. This ensures that the time byte delivered to the
slave read is always valid and it does not change when the read is still in progress on
the bus. The RTC time will change whenever hardware update is in progress, or there is
a software write to the RTC time bytes.
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Datasheet
INTEL [ INTEL ]
