Functional Description
5.20.5
5.20.6
SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, The
ICH10 can generate an interrupt, an SMI#, or a wake event from S1–S5.
SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the ICH10 automatically calculates
and drives CRC at the end of the transmitted packet for write cycles, and will check the
CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The
PEC bit must not be set in the Host Control register if this bit is set, or unspecified
behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at offset 0Ch will be set.
5.20.7
SMBus Slave Interface
The ICH10’s SMBus Slave interface is accessed via the SMBus. The SMBus slave logic
will not generate or handle receiving the PEC byte and will only act as a Legacy Alerting
Protocol device. The slave interface allows the ICH10 to decode cycles, and allows an
external microcontroller to perform specific actions. Key features and capabilities
include:
• Supports decode of three types of messages: Byte Write, Byte Read, and Host
Notify.
• Receive Slave Address register: This is the address that the ICH10 decodes. A
default value is provided so that the slave interface can be used without the
processor having to program this register.
• Receive Slave Data register in the SMBus I/O space that includes the data written
by the external microcontroller.
• Registers that the external microcontroller can read to get the state of the ICH10.
• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due
to the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command
— Bit 16 of the SMI Status Register (Section 13.8.3.13) for all others
Note:
The external microcontroller should not attempt to access the Intel ICH10’s SMBus
slave logic until either:
— 800 milliseconds after both: RTCRST# is high and RSMRST# is high, OR
— The PLTRST# deasserts
If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more
in the middle of a cycle, the ICH10 slave logic's behavior is undefined. This is
interpreted as an unexpected idle and should be avoided when performing
management activities to the slave logic.
Note:
When an external microcontroller accesses the SMBus Slave Interface over the SMBus
a translation in the address is needed to accommodate the least significant bit used for
read/write control. For example, if the ICH10 slave address (RCV_SLVA) is left at 44h
(default), the external micro controller would use an address of 88h/89h (write/read).
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Datasheet
INTEL [ INTEL ]
