Functional Description
5.20.7.1
Format of Slave Write Cycle
The external master performs Byte Write commands to the ICH10 SMBus Slave I/F. The
“Command” field (bits 11:18) indicate which register is being accessed. The Data field
(bits 20:27) indicate the value that should be written to that register.
Table 5-52 has the values associated with the registers.
Table 5-52. Slave Write Registers
Register
Function
Command Register. See Table 5-53 below for legal values written to this
register.
0
1–3
4
Reserved
Data Message Byte 0
Data Message Byte 1
Reserved
5
6–7
8
Reserved
9–FFh
Reserved
NOTE: The external microcontroller is responsible to make sure that it does not update the
contents of the data byte registers until they have been read by the system processor. The
ICH10 overwrites the old value with any new value received. A race condition is possible
where the new value is being written to the register just at the time it is being read. ICH10
will not attempt to cover this race condition (i.e., unpredictable results in this case).
.
Table 5-53. Command Types (Sheet 1 of 2)
Command
Type
Description
0
Reserved
WAKE/SMI#. This command wakes the system if it is not already awake. If
system is already awake, an SMI# is generated.
NOTE: The SMB_WAK_STS bit will be set by this command, even if the system is
already awake. The SMI handler should then clear this bit.
1
Unconditional Powerdown. This command sets the PWRBTNOR_STS bit, and
has the same effect as the Powerbutton Override occurring.
2
3
HARD RESET WITHOUT CYCLING: This command causes a hard reset of the
system (does not include cycling of the power supply). This is equivalent to a write
to the CF9h register with bits 2:1 set to 1, but bit 3 set to 0.
HARD RESET SYSTEM. This command causes a hard reset of the system
(including cycling of the power supply). This is equivalent to a write to the CF9h
register with bits 3:1 set to 1.
4
5
Disable the TCO Messages. This command will disable the Intel ICH10 from
sending Heartbeat and Event messages (as described in Section 5.14). Once this
command has been executed, Heartbeat and Event message reporting can only be
re-enabled by assertion and deassertion of the RSMRST# signal.
6
7
WD RELOAD: Reload watchdog timer.
Reserved
Datasheet
223
INTEL [ INTEL ]
