Functional Description
®
5.22.1
Intel AMT Features
• E-Asset Tag
• OOB HW and SW Inventory Logs
• OOB Alerts
• IDE Redirect
• Serial over LAN for Remote Control
• Remote Diagnostics Execution
• OS Lock-Up Alert
• OS Repair
• Remote BIOS Recovery and Update
®
5.22.2
Intel AMT Requirements
Intel AMT is a platform-level solution that utilizes multiple system components
including:
• Intel AMT-Ready ICH10 SKU
• Intel Gigabit Ethernet PHY (Intel® 82567 Gigabit Platform LAN Connect device)
with Intel Active Management Technology for remote access
• SPI flash memory with 4KB or 8KB sector erase that meets requirements set in
Section 5.23.4 (32 Mb minimum for Intel AMT) to store asset information,
management software code, and logs
• BIOS to provide asset detection and POST diagnostics (BIOS and Intel AMT can
optionally share same flash memory device)
• Familiar ISV software packages to take advantage of Intel AMT’s platform
management capabilities
5.23
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a lower-cost
alternative for system flash versus the Firmware Hub on the LPC bus.
The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In
(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select
(SPI_CS[1:0]#).
The ICH10 supports up to two SPI flash devices using two separate Chip Select pins.
Each SPI flash device can be up to 16 MBytes. The ICH10 SPI interface supports 20
MHz and 33 MHz SPI devices.
Communication on the SPI bus is done with a Master – Slave protocol. The Slave is
connected to the ICH10 and is implemented as a tri-state bus.
Note:
Note:
If option 11 LPC is selected BIOS may still be placed on LPC, but all platforms with
ICH10 (Corporate Only) require SPI flash connected directly to the ICH's SPI bus with a
valid descriptor in order to boot.
When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected
by the ICH10, LPC based BIOS flash is disabled.
Datasheet
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