Functional Description
Table 5-55. Data Values for Slave Read Registers (Sheet 1 of 2)
Register
Bits
Description
Reserved for capabilities indication. Should always return 00h. Future
chips may return another value to indicate different capabilities.
0
7:0
System Power State
1
2:0
000 = S0 001 = S1 010 = Reserved 011 = S3
100 = S4 101 = S5 110 = Reserved 111 = Reserved
7:3
3:0
7:4
Reserved
Reserved
Reserved
2
3
Watchdog Timer current value Note that Watchdog Timer has 10
bits, but this field is only 6 bits. If the current value is greater than
3Fh, ICH10 will always report 3Fh in this field.
5:0
7:6
0
Reserved
1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that
the system cover has probably been opened.
4
1 = BTI Temperature Event occurred. This bit will be set if the Intel
ICH10’s THRM# input signal is at a valid low voltage state. This bit will
be clear if the THRM# input signal is at a valid high voltage state.
NOTE: This bit interprets the behavior if the THRM# pin as active low.
This bit is set independent of the TRM#_POL bit setting.
1
(Consumer
Only)
1 = BTI Temperature Event occurred. This bit will be set if the Intel
ICH10’s THRM# input signal is active. Else this bit will read 0.
NOTE: The THRM# pin is in core well and accurate reflection of the
THRM# pin is dependent on the platform being in S0.
1
(Corporate
Only)
DOA CPU Status. This bit will be 1 to indicate that the processor is
dead
2
1 = SECOND_TO_STS bit set. This bit will be set after the second
time-out (SECOND_TO_STS bit) of the Watchdog Timer occurs.
3
6:4
Reserved. Will always be 0, but software should ignore.
Reflects the value of the GPIO[11]/SMBALERT# pin (and is dependent
upon the value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1,
then the value in this bit equals the level of the GPI[11]/SMBALERT#
pin (high = 1, low = 0).
7
If the GPI_INV[11] bit is 0, then the value of this bit will equal the
inverse of the level of the GPIO[11]/SMBALERT# pin (high = 0,
low = 1).
FWH bad bit. This bit will be 1 to indicate that the FWH read returned
FFh, which indicates that it is probably blank.
5
0
1
2
Reserved
CPU Power Failure Status: ‘1’ if the CPUPWR_FLR bit in the
GEN_PMCON_2 register is set.
INIT# due to receiving Shutdown message: This event is visible
from the reception of the shutdown message until a platform reset is
done if the Shutdown Policy Select bit (SPS) is configured to drive
INIT#. When the SPS bit is configured to generate PLTRST# based on
shutdown, this register bit will always return 0.
3
4
Events on signal will not create a event message
Reserved
Datasheet
225
INTEL [ INTEL ]
