Functional Description
The ICH10 SMBus slave interface only supports Byte Read operation. The external
SMBus master will read the RTC time bytes one after another. It is software’s
responsibility to check and manage the possible time rollover when subsequent time
bytes are read.
For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the
external SMBus master reads the hour as 11, then proceeds to read the minute, it is
possible that the rollover happens between the reads and the minute is read as 0. This
results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless
it is certain that rollover will not occur, software is required to detect the possible time
rollover by reading multiple times such that the read time bytes can be adjusted
accordingly if needed.
5.20.7.4
Format of Host Notify Command
The ICH10 tracks and responds to the standard Host Notify command as specified in
the System Management Bus (SMBus) Specification, Version 2.0. The host address for
this command is fixed to 0001000b. If the ICH10 already has data for a previously-
received host notify command which has not been serviced yet by the host software (as
indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address
byte of the protocol. This allows the host to communicate non-acceptance to the
master and retain the host notify address and data values for the previous cycle until
host software completely services the interrupt.
Note:
Host software must always clear the HOST_NOTIFY_STS bit after completing any
necessary reads of the address and data registers.
Table 5-56 shows the Host Notify format.
Table 5-56. Host Notify Format
Bit
Description
Driven By
Comment
1
8:2
9
Start
External Master
SMB Host Address — 7 bits External Master
Always 0001_000
Write
External Master
Intel® ICH10
Always 0
ICH10 NACKs if HOST_NOTIFY_STS is
1
10
ACK (or NACK)
Indicates the address of the master;
loaded into the Notify Device Address
Register
17:11 Device Address – 7 bits
External Master
7-bit-only address; this bit is inserted
to complete the byte
18
19
Unused — Always 0
ACK
External Master
ICH10
Loaded into the Notify Data Low Byte
Register
27:20 Data Byte Low — 8 bits
28 ACK
36:29 Data Byte High — 8 bits
External Master
ICH10
Loaded into the Notify Data High Byte
Register
External Master
37
38
ACK
ICH10
Stop
External Master
Datasheet
227
INTEL [ INTEL ]
