Functional Description
5.20.4
Interrupts / SMI#
The ICH10 SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the
SMBUS_SMI_EN bit (Device 31:Function 0:Offset 40h:bit 1).
Table 5-50 and Table 5-51 specify how the various enable bits in the SMBus function
control the generation of the interrupt, Host and Slave SMI, and Wake internal signals.
The rows in the tables are additive, which means that if more than one row is true for a
particular scenario then the Results for all of the activated rows will occur.
Table 5-49. Enable for SMBALERT#
INTREN (Host
SMB_SMI_EN (Host
SMBALERT_DIS
(Slave Command
I/O Register,
Control I/O
Register, Offset
02h, Bit 0)
Configuration Register,
D31:F3:Offset 40h,
Bit 1)
Event
Result
Offset 11h, Bit 2)
X
X
1
X
1
0
X
0
0
Wake generated
SMBALERT#
asserted low
(always reported
in Host Status
Register, Bit 5)
Slave SMI#
generated
(SMBUS_SMI_STS)
Interrupt generated
Table 5-50. Enables for SMBus Slave Write and SMBus Host Events
INTREN (Host Control
I/O Register, Offset
02h, Bit 0)
SMB_SMI_EN (Host
Configuration Register,
D31:F3:Offset 40h, Bit1)
Event
Event
Wake generated when asleep.
Slave SMI# generated when awake
(SMBUS_SMI_STS).
Slave Write to Wake/
SMI# Command
X
X
X
X
Slave Write to
SMLINK_SLAVE_SMI
Command
Slave SMI# generated when in the
S0 state (SMBUS_SMI_STS)
0
1
1
X
0
1
None
Any combination of
Host Status Register
[4:1] asserted
Interrupt generated
Host SMI# generated
Table 5-51. Enables for the Host Notify Command
HOST_NOTIFY_INTREN
(Slave Control I/O Register,
Offset 11h, bit 0)
SMB_SMI_EN (Host
Config Register,
D31:F3:Off40h, Bit 1) Register, Offset 11h, bit 1)
HOST_NOTIFY_WKEN
(Slave Control I/O
Result
0
X
1
X
X
0
0
1
X
None
Wake generated
Interrupt generated
Slave SMI#
1
1
X
generated
(SMBUS_SMI_STS)
Datasheet
221
INTEL [ INTEL ]
