Functional Description
5.13.11 Clock Generators
The clock generator is expected to provide the frequencies shown in Table 5-39.
Table 5-39. Intel® ICH10 Clock Inputs
Clock
Domain
Frequency
Source
Usage
100 MHz
MainClock Used by SATA controller. Stopped in S3 – S based on
Generator SLP_S3# assertion.
SATA_CLK
Differential
100 MHz
MainClock Used by DMI and PCI Express*. Stopped in S3 – S5
Generator based on SLP_S3# assertion.
DMI_CLK
PCICLK
Differential
MainClock Free-running PCI Clock to ICH10. Stopped in S3 – S5
Generator based on SLP_S3# assertion.
33 MHz
Used by USB controllers and Intel High Definition
Audio controller. Stopped in S3 – S5 based on
SLP_S3# assertion.
MainClock
Generator
CLK48
CLK14
48.000 MHz
14.318 MHz
MainClock Used by ACPI timers. Stopped in S3 – S5 based on
Generator SLP_S3# assertion.
Platform
LAN
Connect
LAN Connect Interface and Gigabit LAN Connect
Interface. Control policy is determined by the clock
source.
5 to
62.5 MHz
GLAN_CLK
®
5.13.11.1 Clock Control Signals from Intel ICH10 to Clock
Synthesizer
The clock generator is assumed to have direct connect from the following ICH10
signals:
• STP_CPU#: Stops processor clocks in C3 and C4 states
• STP_PCI#: Stops system PCI clocks (not the ICH10 free-running 33 MHz clock) due
to CLKRUN# protocol
• SLP_S3#: Expected to drive clock chip PWRDOWN (through inverter), to stop
clocks in S3 to S5.
164
Datasheet
INTEL [ INTEL ]
