Functional Description
5.13.12 Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various
hardware mechanisms. The scheme relies on the concept of detecting when individual
subsystems are idle, detecting when the whole system is idle, and detecting when
accesses are attempted to idle subsystems.
However, the operating system is assumed to be at least APM enabled. Without APM
calls, there is no quick way to know when the system is idle between keystrokes. The
ICH10 does not support burst modes.
5.13.12.1 APM Power Management
The ICH10 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and
Enable register, generates an SMI# once per minute. The SMI handler can check for
system activity by reading the DEVACT_STS register. If none of the system bits are set,
the SMI handler can increment a software counter. When the counter reaches a
sufficient number of consecutive minutes with no activity, the SMI handler can then put
the system into a lower power state.
If there is activity, various bits in the DEVACT_STS register will be set. Software clears
the bits by writing a 1 to the bit position.
The DEVACT_STS register allows for monitoring various internal devices, or Super I/O
devices (SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions
on LPC or PCI. Other PCI activity can be monitored by checking the PCI interrupts.
5.13.13 Reset Behavior
When a reset is triggered, the ICH10 will send a warning message to the (G)MCH to
allow the (G)MCH to attempt to complete any outstanding memory cycles and put
memory into a safe state before the platform is reset. When the (G)MCH is ready, it will
send an acknowledge message to the ICH10. Once the message is received the ICH10
asserts PLTRST#.
The ICH10 does not require an acknowledge message from the (G)MCH to trigger
PLTRST#. A global reset will occur after 4 seconds if an acknowledge from the (G)MCH
is not received.
Note:
When the ICH10 causes a reset by asserting PLTRST# its output signals will go to their
reset states as defined in Chapter 3.
A reset in which the host platform is reset and PLTRST# is asserted is called a Host
Reset or Host Partition Reset. Depending on the trigger a host reset may also result in
power cycling see Chapter 5-40 for details. If a host reset is triggered and the ICH10
times out before receiving an acknowledge message from the (G)MCH a Global Reset
with power cycle will occur. A reset in which the host and ME partitions of the platform
are reset is called a Global Reset.
Datasheet
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INTEL [ INTEL ]
