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319973-003 参数 Datasheet PDF下载

319973-003图片预览
型号: 319973-003
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔I / O控制器中枢10 [Intel I/O Controller Hub 10]
分类和应用: 控制器
文件页数/大小: 840 页 / 5889 K
品牌: INTEL [ INTEL ]
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Functional Description  
5.13.10 System Power Supplies, Planes, and Signals  
5.13.10.1 Power Plane Control with SLP_S3#, SLP_S4#, SLP_S5# and SLP_M#  
The SLP_S3# output signal can be used to cut power to the system core supply, since it  
only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power  
must be maintained to the ICH10 suspend well, and to any other circuits that need to  
generate Wake signals from the Suspend-to-RAM state. During S3 (Suspend-to-RAM)  
all signals attached to powered down plans will be tri-stated or driven low, unless they  
are pulled via a pull-up resistor.  
Cutting power to the core may be done via the power supply, or by external FETs on the  
motherboard.  
The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core  
supply, as well as power to the system memory, since the context of the system is  
saved on the disk. Cutting power to the memory may be done via the power supply, or  
by external FETs on the motherboard.  
The SLP_S4# output signal is used to remove power to additional subsystems that are  
powered during SLP_S3#.  
SLP_S5# output signal can be used to cut power to the system core supply, as well as  
power to the system memory, since the context of the system is saved on the disk.  
Cutting power to the memory may be done via the power supply, or by external FETs  
on the motherboard.  
SLP_M# output signal can be used to cut power to the Controller Link, Clock chip and  
SPI flash on a platform that supports Intel AMT.  
5.13.10.2 SLP_S4# and Suspend-To-RAM Sequencing  
The system memory suspend voltage regulator is controlled by the Glue logic. The  
SLP_S4# signal should be used to remove power to system memory rather than the  
SLP_S5# signal. The SLP_S4# logic in the ICH10 provides a mechanism to fully cycle  
the power to the DRAM and/or detect if the power is not cycled for a minimum time.  
Note:  
To use the minimum DRAM power-down feature that is enabled by the SLP_S4#  
Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled  
by the SLP_S4# signal.  
162  
Datasheet  
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