Functional Description
Table 5-40 shows the various reset triggers.
Table 5-40. Causes of Host and Global Resets
Host Reset
without
Power
Host Reset
with Power
Cycle
Global
Reset with
Power Cycle
Trigger
Cycle
Write of 0Eh to CF9h Register when Global Reset
bit = 0b (D31:F0:ACh:20)
No
Yes
No
Yes
No
No
No (Note 1)
No (Note 1)
Yes
Write of 06h to CF9h Register when Global Reset
bit = 0b
Write of 06h or 0Eh to CF9h register when Global
Reset bit = 1b
SYS_RESET# Asserted and CF9h bit 3 = 0
SYS_RESET# Asserted and CF9h bit 3 = 1
Yes
No
No
No (Note 1)
No (Note 1)
Yes
SMBus Slave Message received for Reset with
Power Cycle
No
Yes
No (Note 1)
SMBus Slave Message received for Reset without
Power Cycle
Yes
Yes
No
No
No
No
No (Note 1)
No (Note 1)
Yes (Note 2)
TCO Watchdog timer reaches zero two times
Power Failure: PWROK signal or VRMPWRGD signal
goes inactive or RSMRST# asserts
Special shutdown cycle from CPU causes CF9h-like
PLTRST# and CF9h Global Reset bit = 1
No
No
Yes
No
No
Yes
Special shutdown cycle from CPU causes CF9h-like
PLTRST# and CF9h bit 3 = 1
No
No (Note 2)
No (Note 1)
No (Note 1)
Special Shutdown Cycle from CPU causes CF9h-
like PLTRST# and CF9h Global Reset bit = 0
Yes
Yes
Intel® Management Engine Triggered Host Reset
without power cycle
Intel Management Engine Triggered Host Reset
with power cycle
No
No
No
Yes
No
No (Note 1)
Yes
Intel Management Engine Triggered Global Reset
Intel Management Engine Initiated Host Reset with
power down
Yes (Note 3) No (Note 1)
Intel Management Engine Watchdog Timer
Power Management Watchdog Timer
No
No
Yes (Note 4) No (Note 1)
Yes (Note 4) No (note 1)
NOTES:
1.
Trigger will result in Global Reset with power cycle if the acknowledge message is not
received by the ICH10.
2.
3.
4.
ICH10 does not send warning message to (G)MCH, reset occurs without delay.
ICH10 waits for enabled wake event to complete reset.
System stays in S5 state.
166
Datasheet
INTEL [ INTEL ]
