Functional Description
5.13.9.2
PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written in order for
the PIC to operate properly. Therefore, there is no need to return these values in ALT
access mode. When reading PIC registers from 20h and A0h, the reserved bits shall
return the values listed in Table 5-37.
Table 5-37. PIC Reserved Bits Return Values
PIC Reserved Bits
Value Returned
ICW2(2:0)
ICW4(7:5)
ICW4(3:2)
ICW4(0)
000
000
00
0
OCW2(4:3)
OCW3(7)
00
0
Reflects bit 6
01
OCW3(5)
OCW3(4:3)
5.13.9.3
Read Only Registers with Write Paths in ALT Access Mode
The registers described in Table 5-38 have write paths to them in ALT access mode.
Software restores these values after returning from a powered down state. These
registers must be handled special by software. When in normal mode, writing to the
base address/count register also writes to the current address/count register.
Therefore, the base address/count must be written first, then the part is put into ALT
access mode and the current address/count register is written.
Table 5-38. Register Write Accesses in ALT Access Mode
I/O Address
Register Write Value
08h
D0h
DMA Status Register for channels 0–3.
DMA Status Register for channels 4–7.
Datasheet
161
INTEL [ INTEL ]
