Functional Description
5.13.10.3 PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid.
PWROK should go active no sooner than 99 ms after Vcc3_3 and Vcc1_5 have reached
their nominal values. PWROK must not glitch, even if RSMRST# is low.
Note:
1. SYSRESET# is recommended for implementing the system reset button. This saves
external logic that is needed if the PWROK input is used. Additionally, it allows for
better handling of the SMBus and processor resets, and avoids improperly
reporting power failures.
2. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that
are less than one RTC clock period may not be detected by the ICH10.
3. In the case of true PWROK failure, PWROK will go low before VRMPWRGD.
4. When PWROK goes inactive, a host power cycle reset will occur. A host power cycle
is the assertion of SLP_S3#, SLP_S4#, and SLP_S5#, and the deassertion of these
signals 3-5 seconds later. The Intel Management Engine remains powered
throughout this cycle.
5.13.10.4 CPUPWRGD Signal
This signal is connected to the processor’s VRM via the VRMPWRGD signal and is
internally AND’d with the PWROK signal that comes from the system power supply.
5.13.10.5 VRMPWRGD Signal
VRMPWRGD is an input from the regulator indicating that all of the outputs from the
regulator are on and within specification. Platforms that use the VRMPWRGD signal to
start the clock chip PLLs assume that it asserts milliseconds before PWROK in order to
provide valid clocks in time for the PWROK rising.
Note:
When VRMPWRGD goes inactive, a host power cycle reset will occur. A host power cycle
is the assertion of SLP_S3#, SLP_S4#, and SLP_S5#, and the deassertion of these
signals 3-5 seconds later. The Intel Management Engine remains powered throughout
this cycle.
5.13.10.6 DRAMPWROK Signal (Corporate Only)
The DRAMPWROK output is sent to the (G)MCH as an indication of when DRAM power is
turned off. The (G)MCH uses this information as one of the conditions for asserting the
DDR3 Reset signal.
The ICH10’s open-drain buffer pulls the signal low when SLP_S4# is asserted and
CLPWROK deasserted.
Datasheet
163
INTEL [ INTEL ]
