Functional Description
5.14.1.2
Handling an Intruder
The ICH10 has an input signal, INTRUDER#, that can be attached to a switch that is
activated by the system’s case being open. This input has a two RTC clock debounce. If
INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the
TCO_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the ICH10
to cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a
transition to the S5 state by writing to the SLP_EN bit.
The software can also directly read the status of the INTRUDER# signal (high or low) by
clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI
if the intruder function is not required.
If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written
as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input signal goes
inactive. Note that this is slightly different than a classic sticky bit, since most sticky
bits would remain active indefinitely when the signal goes active and would
immediately go inactive when a 1 is written to the bit.
Note:
Note:
The INTRD_DET bit resides in the ICH10’s RTC well, and is set and cleared
synchronously with the RTC clock. Thus, when software attempts to clear INTRD_DET
(by writing a 1 to the bit location) there may be as much as two RTC clocks (about
65 µs) delay before the bit is actually cleared. Also, the INTRUDER# signal should be
asserted for a minimum of 1 ms to ensure that the INTRD_DET bit will be set.
If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET
bit, the bit remains set and the SMI is generated again immediately. The SMI handler
can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal
goes inactive and then active again, there will not be further SMIs, since the
INTRD_SEL bits would select that no SMI# be generated.
5.14.1.3
5.14.1.4
Detecting Improper Firmware Hub Programming
The ICH10 can detect the case where the BIOS flash is not programmed. This results in
the first instruction fetched to have a value of FFh. If this occurs, the ICH10 sets the
BAD_BIOS bit. The BIOS flash may reside in FWH or flash on the SPI bus.
Heartbeat and Event Reporting via SMLink/SMBus
Heartbeat and event reporting via SMLink/SMBus is no longer supported. The Intel AMT
logic in ICH10 can be programmed to generate an interrupt to the Intel Management
Engine when an event occurs. The Intel Management Engine will poll the TCO registers
to gather appropriate bits to send the event message to the Gigabit Ethernet controller,
if Intel Management Engine is programmed to do so.
The Intel Management Engine is responsible for sending ASF 2.0 messages if
programmed to do so.
In Advanced TCO BMC mode, the external micro-controller (BMC) accesses the TCO
info through SMBus.
168
Datasheet
INTEL [ INTEL ]
