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319973-003 参数 Datasheet PDF下载

319973-003图片预览
型号: 319973-003
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔I / O控制器中枢10 [Intel I/O Controller Hub 10]
分类和应用: 控制器
文件页数/大小: 840 页 / 5889 K
品牌: INTEL [ INTEL ]
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Functional Description  
5.14  
System Management (D31:F0)  
The ICH10 provides various functions to make a system easier to manage and to lower  
the Total Cost of Ownership (TCO) of the system. In addition, ICH10 provides  
integrated ASF Management support, requires use of SPI Flash and Intel Management  
Engine firmware. Features and functions can be augmented via external A/D converters  
and GPIO, as well as an external microcontroller.  
The following features and functions are supported by the ICH10:  
• Processor present detection  
— Detects if processor fails to fetch the first instruction after reset  
• Various Error detection (such as ECC Errors) indicated by host controller  
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt  
• Intruder Detect input  
— Can generate TCO interrupt or SMI# when the system cover is removed  
— INTRUDER# allowed to go active in any power state, including G3  
• Detection of bad BIOS Flash (FWH or Flash on SPI) programming  
— Detects if data on first read is FFh (indicates that BIOS flash is not  
programmed)  
• Ability to hide a PCI device  
— Allows software to hide a PCI device in terms of configuration space through  
the use of a device hide register (See Section 10.1.75)  
Note:  
Voltage ID from the processor can be read via GPI signals. ASF functionality with the  
integrated ICH10 ASF controller requires a correctly configured system, including an  
appropriate SKU of the ICH10 (see Section 1.3), (G)MCH with Intel Management  
Engine, Intel Management Engine Firmware, system BIOS support, and appropriate  
Platform LAN Connect Device.  
5.14.1  
Theory of Operation  
The System Management functions are designed to allow the system to diagnose failing  
subsystems. The intent of this logic is that some of the system management  
functionality can be provided without the aid of an external microcontroller.  
5.14.1.1  
Detecting a System Lockup  
When the processor is reset, it is expected to fetch its first instruction. If the processor  
fails to fetch the first instruction after reset, the TCO timer times out twice and the  
ICH10 asserts PLTRST#.  
Datasheet  
167  
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