Functional Description
Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)
Restore Data
Restore Data
I/O
Addr
# of
Rds
I/O
Addr
# of
Rds
Access
Data
Access
Data
DMA Chan 6 base count low
byte
1
2
3
4
5
6
DMA Chan 0–3 Command2
DMA Chan 0–3 Request
1
2
1
2
1
2
CAh
CCh
CEh
2
2
2
DMA Chan 6 base count
high byte
DMA Chan 0 Mode:
Bits(1:0) = 00
DMA Chan 7 base address
low byte
08h
6
DMA Chan 1 Mode:
Bits(1:0) = 01
DMA Chan 7 base address
high byte
DMA Chan 2 Mode:
Bits(1:0) = 10
DMA Chan 7 base count low
byte
DMA Chan 3 Mode: Bits(1:0)
= 11.
DMA Chan 7 base count
high byte
1
2
PIC ICW2 of Master controller
PIC ICW3 of Master controller
1
2
DMA Chan 4–7 Command2
DMA Chan 4–7 Request
DMA Chan 4 Mode:
Bits(1:0) = 00
3
4
5
6
PIC ICW4 of Master controller
3
4
5
6
PIC OCW1 of Master
controller1
DMA Chan 5 Mode:
Bits(1:0) = 01
D0h
6
PIC OCW2 of Master
controller
DMA Chan 6 Mode:
Bits(1:0) = 10
PIC OCW3 of Master
controller
DMA Chan 7 Mode:
Bits(1:0) = 11.
20h
12
7
8
9
PIC ICW2 of Slave controller
PIC ICW3 of Slave controller
PIC ICW4 of Slave controller
PIC OCW1 of Slave
controller1
10
11
12
PIC OCW2 of Slave controller
PIC OCW3 of Slave controller
NOTES:
1.
2.
The OCW1 register must be read before entering ALT access mode.
Bits 5, 3, 1, and 0 return 0.
160
Datasheet
INTEL [ INTEL ]
