Functional Description
5.13.9.1
Write Only Registers with Read Paths in ALT Access Mode
The registers described in Table 5-36 have read paths in ALT access mode. The access
number field in the table indicates which register will be returned per access to that
port.
Table 5-36. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)
Restore Data
Restore Data
I/O
Addr
# of
Rds
I/O
Addr
# of
Rds
Access
Data
Access
Data
DMA Chan 0 base address
low byte
Timer Counter 0 status, bits
[5:0]
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
3
4
5
6
7
00h
01h
02h
03h
04h
05h
06h
07h
2
2
2
2
2
2
2
2
DMA Chan 0 base address
high byte
Timer Counter 0 base count
low byte
DMA Chan 0 base count low
byte
Timer Counter 0 base count
high byte
DMA Chan 0 base count high
byte
Timer Counter 1 base count
low byte
40h
7
DMA Chan 1 base address
low byte
Timer Counter 1 base count
high byte
DMA Chan 1 base address
high byte
Timer Counter 2 base count
low byte
DMA Chan 1 base count low
byte
Timer Counter 2 base count
high byte
DMA Chan 1 base count high
byte
Timer Counter 1 status, bits
[5:0]
41h
42h
70h
1
1
1
DMA Chan 2 base address
low byte
Timer Counter 2 status, bits
[5:0]
DMA Chan 2 base address
high byte
Bit 7 = NMI Enable,
Bits [6:0] = RTC Address
DMA Chan 2 base count low
byte
DMA Chan 5 base address
low byte
1
2
1
2
1
2
C4h
C6h
C8h
2
2
2
DMA Chan 2 base count high
byte
DMA Chan 5 base address
high byte
DMA Chan 3 base address
low byte
DMA Chan 5 base count low
byte
DMA Chan 3 base address
high byte
DMA Chan 5 base count
high byte
DMA Chan 3 base count low
byte
DMA Chan 6 base address
low byte
DMA Chan 3 base count high
byte
DMA Chan 6 base address
high byte
Datasheet
159
INTEL [ INTEL ]
