Functional Description
5.13.8.2
RI# (Ring Indicator)
The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states.
Table 5-35 shows when the wake event is generated or ignored in different states. If in
the G0/S0/Cx states, the ICH10 generates an interrupt based on RI# active, and the
interrupt will be set up as a Break event.
Table 5-35. Transitions Due to RI# Signal
Present State
Event
RI_EN
Event
S0
RI# Active
X
Ignored
0
1
Ignored
S1–S5
RI# Active
Wake Event
Note:
Filtering/Debounce on RI# will not be done in ICH10. Can be in modem or external.
5.13.8.3
PME# (PCI Power Management Event)
The PME# signal comes from a PCI device to request that the system be restarted. The
PME# signal can generate an SMI#, SCI, or optionally a Wake event. The event occurs
when the PME# signal goes from high to low. No event is caused when it goes from low
to high.
There is also an internal PME_B0 bit. This is separate from the external PME# signal
and can cause the same effect.
5.13.8.4
SYS_RESET# Signal
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the
ICH10 attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to
go idle. If the SMBus is idle when the pin is detected active, the reset occurs
immediately; otherwise, the counter starts. If at any point during the count the SMBus
goes idle the reset occurs. If, however, the counter expires and the SMBus is still active,
a reset is forced upon the system even though activity is still occurring.
Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the
SYSRESET# input remains asserted or not. It cannot occur again until SYS_RESET#
has been detected inactive after the debounce logic, and the system is back to a full S0
state with PLTRST# inactive. Note that if bit 3 of the CF9h I/O register is set then
SYS_RESET# will result in a full power cycle reset.
5.13.8.5
THRMTRIP# Signal
If THRMTRIP# goes active, the processor is indicating an overheat condition, and the
ICH10 immediately transitions to an S5 state. However, since the processor has
overheated, it does not respond to the ICH10’s STPCLK# pin with a stop grant special
cycle. Therefore, the ICH10 does not wait for one. Immediately upon seeing
THRMTRIP# low, the ICH10 initiates a transition to the S5 state, drive SLP_S3#,
SLP_S4#, SLP_S5# low, and set the CTS bit. The transition looks like a power button
override.
When a THRMTRIP# event occurs, the ICH10 will power down immediately without
following the normal S0 -> S5 path. The ICH10 will immediately drive SLP_S3#,
SLP_S4#, and SLP_S5# low after sampling THRMTRIP# active.
If the processor is running extremely hot and is heating up, it is possible (although very
unlikely) that components around it, such as the ICH10, are no longer executing cycles
properly. Therefore, if THRMTRIP# goes active, and the ICH10 is relying on state
machine logic to perform the power down, the state machine may not be working, and
the system will not power down.
Datasheet
157
INTEL [ INTEL ]
