Functional Description
Power Button Override Function (ICH10 Consumer Only)
If PWRBTN# is observed active for at least four consecutive seconds, the state machine
unconditionally transitions to the G2/S5 state, regardless of present state (S0-S4),
even if PWROK is not active. In this case, the transition to the G2/S5 state does not
depend on any particular response from the processor (e.g., a Stop-Grant cycle), nor
any similar dependency from any other subsystem. The PWRBTN# status is readable to
check if the button is currently being pressed or has been released. The status is taken
after the de-bounce, and is readable via the PWRBTN_LVL bit.
Note:
Note:
The 4-second PWRBTN# assertion should only be used if a system lock-up has
occurred.
The 4-second timer starts counting when the ICH10 is in a S0 state. If the PWRBTN#
signal is asserted and held active when the system is in a suspend state (S1-S5), the
assertion causes a wake event. Once the system has resumed to the S0 state, the 4-
second timer starts.
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event.
Power Button Override Function (ICH10 Corporate Only)
If PWRBTN# is observed active for at least four consecutive seconds when in S0/1 or at
least nine consecutive seconds when in S3-S4, the state machine unconditionally
transitions to the G2/S5 state, even if PWROK is not active. In this case, the transition
to the G2/S5 state does not depend on any particular response from the processor
(e.g., a Stop-Grant cycle), nor any similar dependency from any other subsystem. The
PWRBTN# status is readable to check if the button is currently being pressed or has
been released. The status is taken after the de-bounce, and is readable via the
PWRBTN_LVL bit.
Note:
Note:
A 4 to 9 second PWRBTN# assertion should only be used if a system lock-up has
occurred.
The power button override timer starts counting when PWRBTN# is asserted and will be
set to 4 seconds when the platform is in S0/S1 and 9 seconds when the platform is in
S3-S4 in order to trigger a power button override event.
During the time that the SLP_S3#/SLP_S4# signal is stretched for the minimum
assertion width (if enabled in D31:F0:A4h), a Power Button is not wake event. For this
reason, the ICH10 Corporate will always extend the power button override timer to 9
seconds when in S3/S4 to allow for a wake event that is delayed by SLP_S3#/SLP_S4#
stretching to be observed before accidentaly triggering a power button override event.
Sleep Button
The Advanced Configuration and Power Interface, Version 2.0b defines an optional
Sleep button. It differs from the power button in that it only is a request to go from S0
to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the
Sleep Button cannot.
Although the ICH10 does not include a specific signal designated as a Sleep Button,
one of the GPIO signals can be used to create a “Control Method” Sleep Button. See the
Advanced Configuration and Power Interface, Version 2.0b for implementation details.
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Datasheet
INTEL [ INTEL ]
