Functional Description
5.13.7.3
THRM# Override Software Bit
The FORCE_THTL bit allows the BIOS to force passive cooling, independent of the ACPI
software (which uses the THTL_EN and THTL_DTY bits). If this bit is set, the ICH10
starts throttling using the ratio in the THRM_DTY field.
When this bit is cleared the ICH10 stops throttling, unless the THTL_EN bit is set
(indicating that ACPI software is attempting throttling).
If both the THTL_EN and FORCE_THTL bits are set, then the ICH should use the duty
cycle defined by the THRM_DTY field, not the THTL_DTY field.
5.13.7.4
Active Cooling
Active cooling involves fans. The GPIO signals from the ICH10 can be used to turn on/
off a fan.
5.13.8
Event Input Signals and Their Usage
The ICH10 has various input signals that trigger specific events. This section describes
those signals and how they should be used.
5.13.8.1
PWRBTN# (Power Button)
The ICH10 PWRBTN# signal operates as a “Fixed Power Button” as described in the
Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16
ms de-bounce on the input. The state transition descriptions are included in Table 5-34.
Note that the transitions start as soon as the PWRBTN# is pressed (but after the
debounce logic), and does not depend on when the Power Button is released.
Note:
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled), the Power Button is not a wake event. Refer to Power Button Override
Function section below for further detail.
Table 5-34. Transitions Due to Power Button
Present
Event
Transition/Action
Comment
State
SMI# or SCI generated
(depending on SCI_EN,
PWRBTN_INIT_EN,
PWRBTN_EN and
Software typically initiates a
Sleep state
S0/Cx
PWRBTN# goes low
GLB_SMI_EN)
Wake Event. Transitions to
S0 state
S1–S5
G3
PWRBTN# goes low
PWRBTN# pressed
Standard wakeup
No effect since no power
Not latched nor detected
None
PWRBTN# held low
for at least 4
consecutive seconds
No dependence on processor
(e.g., Stop-Grant cycles) or
any other subsystem
Unconditional transition to
S5 state
S0–S4
Datasheet
155
INTEL [ INTEL ]
