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319537-003US 参数 Datasheet PDF下载

319537-003US图片预览
型号: 319537-003US
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔系统控制器中心 [Intel System Controller Hub]
分类和应用: 控制器
文件页数/大小: 450 页 / 2593 K
品牌: INTEL [ INTEL ]
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Memory Controller (D0:F0)  
8 Memory Controller (D0:F0)  
8.1  
Functional Overview  
8.1.1  
DRAM Frequencies and Data Rates  
To reduce design complexity and clock network power, the Intel® SCH maintains a  
fixed relationship to the FSB clock frequency. The FSB frequency can be 100 MHz or  
133 MHz, resulting in support of the following clock frequencies and data rates for  
DRAM.  
FSB Clock  
DRAM Clock  
DRAM Data Rate  
DRAM Type  
Peak Bandwidth  
100 MHz  
133 MHz  
200 MHz  
266 MHz  
400 MT/s  
533 MT/s  
DDR2  
DDR2  
3.2 GB/s  
4.2 GB/s  
8.1.2  
DRAM Command Scheduling  
The Intel® SCH memory controller operates at the common core clock, which is one  
half the DDR2 memory clock frequency, or ¼ the DDR data rate. To provide efficient  
scheduling, the controller is capable of scheduling two operations in the controller core  
clock to be able to issue a command every memory clock (where scheduling rules for  
the memory devices allow).  
The memory controller operates on up to two requests at a time to provide pipelining  
for memory commands where possible. It will issue page management commands  
(activates and precharges) out of order for the later request, but will always service  
reads and writes (CAS operations) in the order in which they were received by the  
controller. This provides efficient scheduling while still maintaining in-order rules for  
compatibility with the FSB IOQ.  
The Intel® SCH never uses any additive latency, which is provided for in DDR2 to  
create a posted CAS effect and improve scheduling efficiency in some memory  
systems.  
8.1.3  
Page Management  
The memory controller is capable of closing open pages after the pages have been idle  
for a configurable period of time. This benefits the system for both power and  
performance (when properly configured). From a performance standpoint, it helps  
since it can reduce the number of page misses encountered. From a power perspective,  
it allows the memory devices to reach the precharge power management state (power  
down when all banks are closed), which has better power saving characteristics on  
most memory devices than when the pages are left open and the device is in powered  
down.  
Datasheet  
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