Memory Controller (D0:F0)
Pages that close due to timeout can do so in one of two ways:
• When one or more (but not all) pages in a given rank time out, the pages that have
timed out will close provided the rank is awake and timing rules allow. If the rank is
powered down, it will be powered up to service individual page closures only if
configured to do so. This is not the default behavior; however, this is primarily a
performance benefit and can adversely effect power consumption.
• When all of the open pages in a rank have timed out, the memory controller will
power up to service page closures.
Note:
There is generally a significant power savings by entering the pre-charge powerdown
state versus the active powerdown state that is used by the memory devices when
pages are still open.
Note:
Up to 16 Banks can be independently tracked by the Intel® SCH memory controller.
8.2
DRAM Technologies and Organization
For the Intel® SCH, 512-Mb, 1-Gb and 2-Gb technologies and addressing are
supported for x16 devices. The DRAM sub-system supports a single-channel, 64-bits
wide, with one or two ranks.
Table 20.
DRAM Attributes
Page
Size
Bank
Addr
Row
Addr
Device Size
Width
Banks
Col Addr
512 Mb
X8
X8
1KB
1KB
1KB
2KB
2KB
2KB
4
8
8
4
8
8
BA0-BA1
BA0-BA2
BA0-BA2
BA0-BA1
BA0-BA2
BA0-BA2
A0-A13
A0-A13
A0-A14
A0-A12
A0-A12
A0-A13
A0-A9
A0-A9
A0-A9
A0-A9
A0-A9
A0-A9
1024 Mb
2048 Mb
512 Mb
X8
X16
X16
X16
1024 Mb
2048 Mb
8.2.1
DRAM Address Mapping
System addresses are decoded by the memory controller to map to the rank, bank,
row, and column physical address locations in the populated DRAMs.
8.2.1.1
DRAM Device Address Decode
For any rank, the address range it implements is mapped into the physical address
regions of the devices on that rank. This is addressable by bank (B), row (R), and
column (C) addresses. Once a rank is selected as described above, the range that it is
implementing is mapped into the device’s physical address as described in Table 21.
90
Datasheet
INTEL [ INTEL ]
