Host Bridge (D0:F0)
(Sheet 2 of 2)
Default
and
Bit
Description
Access
0
R/W
SMI on Hot Trip (SMHT):
1 = SMI is generated on a hot trip.
20
19
18
17
16
15
14
13
12
11
10
9
0
R/W
SMI on Aux3 Trip (SMA3T):
1 = SMI is generated on an Aux3 trip.
0
R/W
SMI on Aux2 Trip (SMA2T):
1 = SMI is generated on an Aux2 trip.
0
R/W
SMI on Aux1 Trip (SMA1T):
1 = SMI is generated on an Aux1 trip.
0
R/W
SMI on Aux0 Trip (SMA0T):
1 = SMI is generated on an Aux0 trip.
0
R/W
SCI on EXTTS1# Thermal Sensor Trip (SCE1T):
1 = SCI is generated on an external Thermal Sensor 1 trip.
0
R/W
SCI on EXTTS0# Thermal Sensor Trip (SCE1T):
1 = SCI is generated on an external Thermal Sensor 1 trip.
0
RO
Reserved
0
R/W
SCI on Hot Trip (SCHT):
1 = SCI is generated on a hot trip.
0
R/W
SCI on Aux3 Trip (SCA3T):
1 = SCI is generated on an Aux3 trip.
0
R/W
SCI on Aux2 Trip (SCA2T):
1 = SCI is generated on an Aux2 trip.
0
R/W
SCI on Aux1 Trip (SCA1T):
1 = SCI is generated on an Aux1 trip.
0
R/W
SCI on Aux0 Trip (SCA0T):
1 = SCI is generated on an Aux0 trip.
8
0
RO
7:0
Reserved
86
Datasheet
INTEL [ INTEL ]
