Memory Controller (D0:F0)
8.3
8.4
DRAM Clock Generation
The Intel® SCH contains two differential clock pairs (SM_CK[1:0]/SM_CK[1:0]#) that
are used to support as many as two ranks of memory on the system board.
DDR2 On-Die Termination
The Intel® SCH memory controller interface was designed to operate properly without
on-die termination. This has resulted is significant power savings, both within the
system and within the Intel® SCH. The Intel® SCH contains features to reduce power
consumption in the event SSTL termination is used within the system.
8.5
DRAM Power Management
The Intel® SCH supports memory power management in the following conditions:
• C0–C1: CKE Powerdown
• C2–C6: Dynamic Self-Refresh
• S3: Self-Refresh
8.5.1
CKE Powerdown
The memory controller employs aggressive use of memory power management
features. When a rank is not being accessed, the CKE for that rank is deasserted,
bringing the devices into either an active or precharge powerdown state depending on
whether any pages are still open in the device.
DDR2 supports slow or fast exit from active powerdown. These options must be
configured in the memory devices themselves by BIOS before memory accesses begin.
The slower exit improves power savings when in a low power state but comes at a high
latency cost. Due to the latency cost this can in some cases have the effect of
increasing power consumption if the memory subsystem frequently has to suffer this
delay and is consuming full power on the I/O interface in the process. The Intel® SCH
will not use the slower exit, opting instead to use the active powerdown as a lighter
powerdown mode, but employing page close timers to get to a more power efficient
precharge powerdown state when the pages in the rank have been idle for the
configured time.
8.5.2
Interface High-Impedance
Although the Intel® SCH is designed to operate properly with no SSTL termination, it
provides power saving mechanisms to reduce power consumption if SSTL termination is
used. To save power on an SSTL-terminated DDR2 interface, any output signals that
are not needed for proper memory operation at that time should be tristated (floated).
This is due to the SSTL termination topology which is center-terminated and thus
consumes power whenever a signal is driven high or low.
• When both ranks are powered down, address and command pins are tristated.
• Address and command signals are only enabled when a chip select is asserted,
floating these signals at all other times.
• When a rank is powered down, the corresponding SM_CS# pins are tristated.
• Data and strobe signals are floated. This occurs whenever the data and strobe are
not actively transferring write data (or issuing a preamble or postamble on the
strobes).
• The SM_CK/SM_CK# signals are floated whenever both ranks are in self refresh.
• Static disabling is available for preventing unused signals from ever driving. This is
provided for SM_BS[2:0], SM_MA[14:13], SM_CK[1:0]/SM_CK[1:0]#,
SM_CKE[1:0].
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Datasheet
INTEL [ INTEL ]
