Host Bridge (D0:F0)
7.2.8
Miscellaneous (Port 05h)
Port 05h contains configuration and status registers that don’t specifically belong to
other ports or interfaces.
7.2.8.1
MSR—Mode and Status Register
Offset:
Default Value:
03h
0000000Uh
Attribute:
Size:
RO
32 bits.
Default
Bit
and
Description
Access
0000000h
RO
31:4
Reserved
Core Clock Frequency: This bit indicates the frequency of the core clock
and the FSB and Memory interface frequencies.
-
RO
3
0 = 100-MHz Core clock, 400-MT/s FSB, 400-MT/s DDR
1 = 133-MHz Core clock, 533-MT/s FSB, 533-MT/s DDR
Graphics Frequency: This bit indicates the frequency for the graphics
core clock.
-
RO
2:0
100 = 200 MHz
Others = Reserved
§ §
88
Datasheet
INTEL [ INTEL ]
