Host Bridge (D0:F0)
7.2.7.1
TTB—Thermal Trip Behavior Register
Offset:
Default Value:
B6h
00000000h
Attribute:
Size:
RO, R/W, R/WLO
32 bits
(Sheet 1 of 2)
Default
Bit
and
Description
Access
Internal Thermal Hardware Throttling Enable bit (ITHTE): This is a
master enable for internal thermal sensor-based hardware throttling.
Interrupts are not affected by this bit. This is for Hot Trip throttling only.
0
R/W
31
000b
RO
30:28
Reserved
Catastrophic Shutdown Select (CSS): Chooses which option to take
upon a catastrophic thermal event.
Bit
Definition
00
No external assertions—internal hardware throttling only.
Power-down immediately: SLPRDY#, SLPMODE, and
RSTRDY# are all driven to 0s within 100 µs. This powers off
the platform. A system reboot is required.
01
10
This is the lowest-latency option.
00b
R/W
Request S5: SLPRDY# is asserted after S5-ready; Powers
off the platform after sleep-readiness has been checked by
the Intel® SCH. A system reboot is required. Once the trip
point is reached, SLPRDY# stays asserted even if the trip
deasserts before the platform is shut down.
27:26
This has the longest latency, but allows for transactions to
finish so as to avoid data from being lost/corrupted.
However, there is still no assurance of corruption
prevention, as functionality to enter S5 is not ensured in
the temperature region where catastrophic trip is normally
Reserved
11
Reserved
0
25
24
Reserved
R/WLO
PROCHOT# ENABLE (PHE): When this bit is set, PROCHOT# is asserted
on Aux2 trip.
0 = PROCHOT# is not asserted
0
R/W
1 = PROCHOT# can be asserted on Aux2 trip
PROCHOT# pulse width has a minimum duration of 500 µs to meet the
processor specifications.
0
R/W
SMI on EXTTS1# Thermal Sensor Trip (SME1T):
1 = SMI is generated on an external Thermal Sensor 1 trip.
23
22
21
0
R/W
SMI on EXTTS0# Thermal Sensor Trip (SME1T):
1 = SMI is generated on an external Thermal Sensor 0 trip.
0
RO
Reserved
Datasheet
85
INTEL [ INTEL ]
