Memory Controller (D0:F0)
Table 21.
DRAM Address Decoder
Device Density
1024 Mb 1024 Mb
x16 x8
Topic
512 Mb
x16
512 Mb
x8
2048Mb
x16
2048Mb
x8
Rank Size
Bank Bits
Row Bits
Col Bits
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
256 MB
2
512 MB
2
512 MB
3
1024 MB
3
1024MB
3
1024MB
3
13
10
—
14
13
14
14
15
10
10
10
10
10
—
—
—
—
—
—
—
—
—
—
R14
R13
B2
—
—
—
R13
B2
R12
R11
R10
R9
R8
R7
R6
R5
R4
B1
C9
R3
R2
R1
R0
B0
C8
C7
C6
C5
C4
C3
C2
C1
C0
R13
B2
R12
R11
R10
R9
R8
R7
R6
R5
R4
B1
C9
R3
R2
R1
R0
B0
C8
C7
C6
C5
C4
C3
C2
C1
C0
—
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
B1
C9
R3
R2
R1
R0
B0
C8
C7
C6
C5
C4
C3
C2
C1
C0
B2
R12
R11
R10
R9
R8
R7
R6
R5
R4
B1
C9
R3
R2
R1
R0
B0
C8
C7
C6
C5
C4
C3
C2
C1
C0
R12
R11
R10
R9
R8
R7
R6
R5
R4
B1
C9
R3
R2
R1
R0
B0
C8
C7
C6
C5
C4
C3
C2
C1
C0
R12
R11
R10
R9
R8
R7
R6
R5
R4
B1
C9
R3
R2
R1
R0
B0
C8
C7
C6
A8
C5
A7
C4
A6
C3
A5
C2
A4
C1
A3
C0
NOTE: R = Row address bit. C = Column address bit. B = Bank Select bit (SM_BS[2:0]).
Datasheet
91
INTEL [ INTEL ]
