Memory Controller (D0:F0)
8.5.3
8.5.4
8.5.5
Refresh
The Intel® SCH handles all DRAM refresh operations when the device is not in self-
refresh. To reduce the performance impact of DRAM refreshes, the Intel® SCH waits
until eight refreshes are required and then issues all of these refreshes. This provides
some increase in efficiency (overall lower percentage of impact to the available
bandwidth), but there will also be a longer period of time that the memory will be
unavailable, roughly 8 x tRFC
.
Self-Refresh
Self-refresh can be entered to save power on the memory device and Intel® SCH
power to drive the DDR2 differential clock signals. When the memory is in self-refresh,
the Intel® SCH disables all output signals, except the SM_CKE signals.
The Intel® SCH will enter self refresh as part of the suspend (S3) sequence. It stays in
this the self-refresh state until a resume sequence is initiated.
Dynamic Self-Refresh
In addition, the Intel® SCH can support dynamic self-refresh in C2–C6 states. It wakes
the memory from self-refresh state whenever memory access is needed, then re-enter
self-refresh state as soon as there are no more requests are needed.
8.5.6
DDR2 Voltage
The Intel® SCH supports 1.8-V and 1.5-V DDR2 memory.
Note:
1.5-V DDR2 support is restricted to single rank operation.
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Datasheet
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INTEL [ INTEL ]
