DRAM Controller Registers (D0:F0)
5.1.13
MCHBAR—GMCH Memory Mapped Register Range Base
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
48–4Fh
0000000000000000h
RW/L, RO
64 bits
Size:
This is the base address for the GMCH Memory Mapped Configuration space. There is
no physical memory within this 16 KB window that can be addressed. The 16 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the GMCH MMIO Memory Mapped Configuration space is disabled and
must be enabled by writing a 1 to MCHBAREN [Dev 0, offset48h, bit 0].
Bit
Access &
Default
Description
63:36
35:14
RO
0000000h
Reserved
RW
000000h
GMCH Memory Mapped Base Address (MCHBAR): This field
corresponds to bits 35:14 of the base address GMCH Memory Mapped
configuration space. BIOS will program this register resulting in a base
address for a 16 KB block of contiguous memory address space. This
register ensures that a naturally aligned 16 KB space is allocated.
System Software uses this base address to program the GMCH Memory
Mapped register set.
13:1
0
RO
0000h
Reserved
RW
0b
MCHBAR Enable (MCHBAREN):
0= MCHBAR is disabled and does not claim any memory
1 = MCHBAR memory mapped accesses are claimed and decoded
appropriately
Datasheet
87
INTEL [ INTEL ]
