DRAM Controller Registers (D0:F0)
5.1.11
CAPPTR—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
34h
E0h
RO
8 bits
Size:
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
Bit
Access &
Default
Description
7:0
RO
E0h
Capabilities Pointer (CAPPTR): Pointer to the offset of the first
capability ID register block. In this case the first capability is the
product-specific Capability Identifier (CAPID0).
5.1.12
PXPEPBAR—PCI Express* Egress Port Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
40–47h
0000000000000000h
RW, RO
Size:
64 bits
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4KB window that can be addressed. The 4 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the Egress port MMIO configuration space is disabled and must be
enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0].
Bit
Access &
Default
Description
63:36
35:12
RO
0000000h
Reserved
RW
000000h
PCI Express Egress Port MMIO Base Address (PXPEPBAR): This
field corresponds to bits 35:12 of the base address PCI Express
Egress Port MMIO configuration space. BIOS will program this register
resulting in a base address for a 4 KB block of contiguous memory
address space. This register ensures that a naturally aligned 4 KB
space is allocated within the first 64 GB of addressable memory
space. System Software uses this base address to program the GMCH
MMIO register set.
11:1
0
RO
000h
Reserved
RW
0b
PXPEPBAR Enable (PXPEPBAREN):
0 = PXPEPBAR is disabled and does not claim any memory
1 = PXPEPBAR memory mapped accesses are claimed and decoded
appropriately
86
Datasheet
INTEL [ INTEL ]
