DRAM Controller Registers (D0:F0)
5.1.8
HDR—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
Eh
00h
RO
8 bits
Size:
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Bit
Access &
Default
Description
7:0
RO
00h
PCI Header (HDR): This field always returns 0 to indicate that the
GMCH is a single function device with standard header layout. Reads
and writes to this location have no effect.
5.1.9
SVID—Subsystem Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
2C–2Dh
0000h
RWO
16 bits
Size:
This value is used to identify the vendor of the subsystem.
Bit
Access &
Default
Description
15:0
RWO
0000h
Subsystem Vendor ID (SUBVID): This field should be programmed
during boot-up to indicate the vendor of the system board. After it has
been written once, it becomes read only.
5.1.10
SID—Subsystem Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
2E–2Fh
0000h
RWO
16 bits
Size:
This value is used to identify a particular subsystem.
Bit
Access &
Default
Description
15:0
RWO
0000h
Subsystem ID (SUBID): This field should be programmed during
BIOS initialization. After it has been written once, it becomes read
only.
Datasheet
85
INTEL [ INTEL ]
