DRAM Controller Registers (D0:F0)
5.1.4
PCISTS—PCI Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
6–7h
0090h
RWC, RO
16 bits
Size:
This status register reports the occurrence of error events on Device 0's PCI interface.
Since the GMCH Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
Bit
Access &
Default
Description
15
RWC
0b
Detected Parity Error (DPE):
1= Device received a Poisoned TLP.
14
RWC
0b
Signaled System Error (SSE): Software clears this bit by writing a 1
to it.
1= The GMCH Device 0 generated a SERR message over DMI for any
enabled Device 0 error condition. Device 0 error conditions are
enabled in the PCICMD, ERRCMD, and DMIUEMSK registers. Device
0 error flags are read/reset from the PCISTS, ERRSTS, or DMIUEST
registers.
13
12
RWC
0b
Received Master Abort Status (RMAS): Software clears this bit by
writing a 1 to it.
1 = GMCH generated a DMI request that receives an Unsupported
Request completion packet.
RWC
0b
Received Target Abort Status (RTAS): Software clears this bit by
writing a 1 to it.
1 = GMCH generated a DMI request that receives a Completer Abort
completion packet.
11
RO
0b
Signaled Target Abort Status (STAS): The GMCH will not generate
a Target Abort DMI completion packet or Special Cycle. This bit is not
implemented in the GMCH and is hardwired to a 0.
10:9
RO
00b
DEVSEL Timing (DEVT): These bits are hardwired to "00". Writes to
these bit positions have no affect. Device 0 does not physically connect
to PCI_A. These bits are set to "00" (fast decode) so that optimum
DEVSEL timing for PCI_A is not limited by the GMCH.
8
7
RWC
0b
Master Data Parity Error Detected (DPD):
1 = This bit is set when DMI received a Poisoned completion from the
ICH.
NOTE: This bit can only be set when the Parity Error Enable bit in the
PCI Command register is set.
RO
1b
Fast Back-to-Back (FB2B): This bit is hardwired to 1. Device 0 does
not physically connect to PCI_A. This bit is set to 1 (indicating fast
back-to-back capability) so that the optimum setting for PCI_A is not
limited by the GMCH.
82
Datasheet
INTEL [ INTEL ]
