Manageability Engine (ME) Registers (D3:F0)
9.1.9
HECI_MBAR—HECI MMIO Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
10–17h
0000000000000004h
RO, R/W
64 bits
Size:
This register allocates space for the HECI memory-mapped registers defined in Section
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Bit
Access &
Default
Description
63:4
R/W
Base Address (BA): This field provides the base address of register
00000000
0000000h
memory space.
3
RO
0b
Prefetchable (PF): This bit indicates that this range is not pre-
fetchable
2:1
RO
10b
Type (TP): This field indicates that this range can be mapped
anywhere in 64-bit address space. Note that the (G)MCH only uses
bits 35:4 of the base address field as the (G)MCH only decodes FSB
address bits 35:4.
0
RO
0b
Resource Type Indicator (RTE): This bit indicates a request for
register memory space.
9.1.10
SS—Sub System Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
2C–2Fh
00000000h
R/WO
Size:
32 bits
Bit
Access &
Default
Description
31:16
R/WO
0000h
Subsystem ID (SSID): This field indicates the sub-system
identifier. This field should be programmed by BIOS during boot-up.
Once written, this register becomes Read Only. This field can only be
cleared by PLTRST#.
15:0
R/WO
0000h
Subsystem Vendor ID (SSVID): This field indicates the sub-
system vendor identifier. This field should be programmed by BIOS
during boot-up. Once written, this register becomes Read Only. This
field can only be cleared by PLTRST#.
274
Datasheet
INTEL [ INTEL ]
