Manageability Engine (ME) Registers (D3:F0)
9.1.3
STS—Device Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
6–7h
0010h
RO
Size:
16 bits
Bit
Access &
Default
Description
15
RO
0b
Detected Parity Error (DPE): Not implemented, hardwired to 0.
Signaled System Error (SSE): Not implemented, hardwired to 0.
Received Master-Abort (RMA): Not implemented, hardwired to 0.
Received Target Abort (RTA): Not implemented, hardwired to 0.
Signaled Target-Abort (STA): Not implemented, hardwired to 0.
DEVSEL# Timing (DEVT): These bits are hardwired to 00.
14
13
12
11
10:9
8
RO
0b
RO
0b
RO
0b
RO
0b
RO
00b
RO
0b
Master Data Parity Error Detected (DPD): Not implemented,
hardwired to 0.
7
RO
0b
Fast Back-to-Back Capable (FBC): Not implemented, hardwired to
0.
6
RO
0b
Reserved
5
RO
0b
66 MHz Capable (C66): Not implemented, hardwired to 0.
4
RO
1b
Capabilities List (CL): Indicates the presence of a capabilities list,
hardwired to 1.
3
RO
0b
Interrupt Status (IS): Indicates the interrupt status of the device
(1 = asserted).
2:0
RO
Reserved
000b
Datasheet
271
INTEL [ INTEL ]
