Manageability Engine (ME) Registers (D3:F0)
9.1.11
CAP—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
34h
50h
RO
Size:
8 bits
Bit
Access &
Default
Description
7:0
RO
Capability Pointer (CP): This field indicates the first capability
50h
pointer offset. It points to the PCI power management capability offset.
9.1.12
INTR—Interrupt Information
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
3C–3Dh
0100h
RO, R/W
16 bits
Size:
Bit
Access &
Default
Description
15:8
RO
Interrupt Pin (IPIN): This field indicates the interrupt pin the HECI
01h
host controller uses. The value of 01h selects INTA# interrupt pin.
Note:As HECI is an internal device in the GMCH, the INTA# pin is
implemented as an INTA# message to the ICH8.
7:0
R/W
00h
Interrupt Line (ILINE): Software written value to indicate which
interrupt line (vector) the interrupt is connected to. No hardware
action is taken on this register.
9.1.13
MGNT—Minimum Grant
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
3Eh
00h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Grant (GNT): Not implemented, hardwired to 0.
00h
Datasheet
275
INTEL [ INTEL ]
