Manageability Engine (ME) Registers (D3:F0)
Bit
7
Access &
Default
Description
RO
0b
Wait Cycle Enable (WCC): Not implemented, hardwired to 0.
6
RO
0b
Parity Error Response Enable (PEE): Not implemented, hardwired
to 0.
5
RO
0b
VGA Palette Snooping Enable (VGA): Not implemented,
hardwired to 0.
4
RO
0b
Memory Write and Invalidate Enable (MWIE): Not implemented,
hardwired to 0.
3
RO
0b
Special Cycle Enable (SCE): Not implemented, hardwired to 0.
2
R/W
0b
Bus Master Enable (BME): This bit controls the HECI host
controller's ability to act as a system memory master for data
transfers.
0 = Disable. HECI is blocked from generating MSI to the host
processor.
1 = Enable
When this bit is cleared, HECI bus master activity stops and any
active DMA engines return to an idle condition. This bit is made
visible to firmware through the H_PCI_CSR register, and changes to
this bit may be configured by the H_PCI_CSR register to generate an
ME MSI.
Note that this bit does not block HECI accesses to ME-UMA (i.e.,
writes or reads to the host and ME circular buffers through the read
window and write window registers still cause ME backbone
transactions to ME-UMA).
1
0
R/W
0b
Memory Space Enable (MSE): This bit controls access to the HECI
host controller’s memory mapped register space.
0 = Disable
1 = Enable
RO
0b
I/O Space Enable (IOSE): Not implemented, hardwired to 0.
270
Datasheet
INTEL [ INTEL ]
