Manageability Engine (ME) Registers (D3:F0)
9.1.17
PC—PCI Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
52–53h
C803h
RO
Size:
16 bits
Bit
Access &
Default
Description
15:11
RO
PME_Support (PSUP): This field indicates the states that can
11001b
generate PME#.
HECI can assert PME# from any D-state except D1 or D2 which are
not supported by HECI.
10
9
RO
0b
D2_Support (D2S): The D2 state is not supported for the HECI host
controller.
RO
0b
D1_Support (D1S): The D1 state is not supported for the HECI host
controller.
8:6
5
RO
000b
Aux_Current (AUXC): Reports the maximum Suspend well current
required when in the D3COLD state.
RO
0b
Device Specific Initialization (DSI): This bit indicates whether
device-specific initialization is required.
4
RO
0b
Reserved
3
RO
0b
PME Clock (PMEC): This bit indicates that PCI clock is not required
to generate PME#.
2:0
RO
Version (VS): This bit indicates support for Revision 1.2 of the PCI
011b
Power Management Specification.
Datasheet
277
INTEL [ INTEL ]
