Manageability Engine (ME) Registers (D3:F0)
9.1.7
MLT—Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
Dh
00h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Master Latency Timer (MLT): Not implemented, hardwired to 0.
00h
9.1.8
HTYPE—Header Type
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
Eh
80h
RO
8 bits
Size:
Bit
7
Access &
Default
Description
RO
1b
Multi-Function Device (MFD): This bit indicates the HECI host
controller is part of a multi-function device.
6:0
RO
Header Layout (HL): This field indicates that the HECI host
0000000b
controller uses a target device layout.
Datasheet
273
INTEL [ INTEL ]
