Manageability Engine (ME) Registers (D3:F0)
9.1.4
RID—Revision ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
8h
see description below
RO
Size:
8 bits
Bit
Access &
Default
Description
7:0
RO
see
description
Revision ID (RID): This field indicates stepping of the HECI host
controller. Refer to the Intel® G35 Express Chipset Specification
Update for the value of the Revision ID register.
9.1.5
CC—Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
9–Bh
000000h
RO
Size:
24 bits
Bit
23:16
15:8
7:0
Access &
Default
Description
RO
00h
Base Class Code (BCC): This field indicates the base class code of
the HECI host controller device.
RO
00h
Sub Class Code (SCC): This field indicates the sub class code of the
HECI host controller device.
RO
Programming Interface (PI): This field indicates the programming
00h
interface of the HECI host controller device.
9.1.6
CLS—Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
Ch
00h
RO
8 bits
Size:
Bit
Access &
Default
Description
7:0
RO
Cache Line Size (CLS): Not implemented, hardwired to 0.
00h
272
Datasheet
INTEL [ INTEL ]
