Manageability Engine (ME) Registers (D3:F0)
9.1.18
PMCS—PCI Power Management Control And Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
54–55h
0008h
R/WC, RO, R/W
16 bits
Size:
Bit
Access &
Default
Description
15
R/WC
0b
PME Status (PMES): The PME Status bit in HECI space can be set to
1 by FW performing a write into AUX register to set PMES.
This bit is cleared by host processor writing a 1 to it.
FW cannot clear this bit.
Host processor writes with value 0 have no effect on this bit.
This bit is reset to 0 by MRST#
14:9
8
RO
000000b
Reserved
R/W
0b
PME Enable (PMEE): This read/write bit is controlled by host SW. It
does not directly have an effect on PME events. This bit is reset to 0 by
MRST#.
0 = Disable
1 = Enable
7:4
3
RO
0000b
Reserved
RO
1b
No_Soft_Reset (NSR): This bit indicates that when the HECI host
controller is transitioning from D3hot to D0 due to power state
command; it does not perform an internal reset.
0 = No soft reset
1 = Soft reset
2
RO
0b
Reserved
1:0
R/W
00b
Power State (PS): This field is used both to determine the current
power state of the HECI host controller and to set a new power state.
The values are:
00 = D0 state
11 = D3HOT state
278
Datasheet
INTEL [ INTEL ]
