Manageability Engine (ME) Registers (D3:F0)
Address
Offset
Symbol
Register Name
Default
Value
Access
90–93h
94–97h
98–99h
A0h
MA
Message Signaled Interrupt Message
Address
00000000h
00000000h
0000h
R/W, RO
R/W
MUA
MD
Message Signaled Interrupt Upper
Address (Optional)
Message Signaled Interrupt Message
Data
R/W
HIDM
HECI Interrupt Delivery Mode
00h
R/W
9.1.1
ID—Identifiers
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
0–3h
29848086h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:16
15:0
RO
2984h
Device ID (DID): This register indicates what device number
assigned for the ME subsystem.
RO
Vendor ID (VID): This field indicates Intel is the vendor, assigned
8086h
by the PCI SIG.
9.1.2
CMD—Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/3/0/PCI
4–5h
0000h
RO, R/W
16 bits
Size:
Bit
15:11
10
Access &
Default
Description
RO
00000b
Reserved
R/W
0b
Interrupt Disable (ID): This bit disables this device from
generating PCI line based interrupts. This bit does not have any
effect on MSI operation.
0 = Enable
1 = Disable
9
8
RO
0b
Fast Back-to-Back Enable (FBE): Not implemented, hardwired to
0.
RO
0b
SERR# Enable (SEE): Not implemented, hardwired to 0.
Datasheet
269
INTEL [ INTEL ]
