Manageability Engine (ME) Registers (D3:F0)
9 Manageability Engine (ME)
Registers (D3:F0)
This chapter contains the Manageability Engine registers for Device 3 (D3), Function 0
(0).
9.1
Host Embedded Controller Interface (HECI1)
Configuration Register Details (D3:F0)
Table 9-1. HECI1 Register Address Map (D3:F0)
Address
Offset
Symbol
Register Name
Default
Value
Access
00–03h
04–05h
06–07h
08h
ID
Identifiers
Command
29848086h
0000h
RO
CMD
STS
RID
RO, R/W
RO
Device Status
Revision ID
0010h
See register
description
RO
09–0Bh
0Ch
CC
Class Code
000000h
00h
RO
CLS
Cache Line Size
RO
0Dh
MLT
HTYPE
Master Latency Timer
Header Type
00h
RO
0Eh
80h
RO
10–17h
HECI_MBA
R
HECI MMIO Base Address
0000000000
000004h
RO, R/W
2C–2Fh
34h
SS
Sub System Identifiers
Capabilities Pointer
Interrupt Information
Minimum Grant
00000000h
50h
R/WO
RO
CAP
3C–3Dh
3Eh
INTR
MGNT
MLAT
HFS
PID
0100h
00h
RO, R/W
RO
3Fh
Maximum Latency
Host Firmware Status
00h
RO
40–43h
50–51h
00000000h
8C01h
RO
PCI Power Management Capability
ID
RO
52–53h
54–55h
PC
PCI Power Management Capabilities
C803h
0008h
RO
PMCS
PCI Power Management Control And
Status
R/WC,
RO, R/W
8C–8Dh
8E–8Fh
MID
MC
Message Signaled Interrupt
Identifiers
0005h
0080h
RO
Message Signaled Interrupt Message
Control
RO, R/W
268
Datasheet
INTEL [ INTEL ]
