PCI Express* Registers (D1:F0)
Bit
Access &
Default
Description
1
RWC
0b
Non-Fatal Error Detected (NFED):
0 = Non-Fatal error Not detected.
1 = Non-fatal error(s) were detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the
Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the uncorrectable error mask
register.
0
RWC
0b
Correctable Error Detected (CED):
0 = Correctable error Not detected.
1 = Correctable error(s) were detected. Errors are logged in this
register regardless of whether error reporting is enabled or not in
the Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the correctable error mask
register.
6.1.38
LCAP—Link Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
AC–AFh
02014D01h
RO, RWO
32 bits
Size:
This register indicates PCI Express device specific capabilities.
Bit
Access &
Default
Description
31:24
RO
02h
Port Number (PN): This field indicates the PCI Express port number
for the given PCI Express link. Matches the value in Element Self
Description[31:24].
23:21
20
RO
000b
Reserved
RO
0b
Data Link Layer Link Active Reporting Capable (DLLLARC): For
a Downstream Port, this bit must be set to 1b if the component
supports the optional capability of reporting the DL_Active state of the
Data Link Control and Management State Machine. For a hot-plug
capable Downstream Port (as indicated by the Hot-Plug Capable field
of the Slot Capabilities register), this bit must be set to 1b.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
19
RO
0b
Surprise Down Error Reporting Capable (SDERC): For a
Downstream Port, this bit must be set to 1b if the component
supports the optional capability of detecting and reporting a Surprise
Down error condition.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
192
Datasheet
INTEL [ INTEL ]
