PCI Express* Registers (D1:F0)
6.1.33
PEG_CAPL—PCI Express*-G Capability List
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
A0–A1h
0010h
RO
Size:
16 bits
This register enumerates the PCI Express capability structure.
Bit
Access &
Default
Description
15:8
RO
00h
Pointer to Next Capability (PNC): This value terminates the
capabilities list. The Virtual Channel capability and any other PCI
Express specific capabilities that are reported via this mechanism are
in a separate capabilities list located entirely within PCI Express
Extended Configuration Space.
7:0
RO
Capability ID (CID): Identifies this linked list item (capability
10h
structure) as being for PCI Express registers.
6.1.34
PEG_CAP—PCI Express*-G Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
A2–A3h
0141h
RO, RWO
16 bits
Size:
This register indicates PCI Express device capabilities.
Bit
15:14
13:9
8
Access &
Default
Description
RO
00b
Reserved
RO
00h
Interrupt Message Number (IMN): Not Applicable or
Implemented. Hardwired to 0.
RWO
1b
Slot Implemented (SI):
0 = The PCI Express Link associated with this port is connected to an
integrated component or is disabled.
1 = The PCI Express Link associated with this port is connected to a
slot.
7:4
3:0
RO
4h
Device/Port Type (DPT): Hardwired to 4h to indicate root port of
PCI Express Root Complex.
RO
1h
PCI Express Capability Version (PCI EXPRESS*CV): Hardwired
to 1 as it is the first version.
188
Datasheet
INTEL [ INTEL ]
