PCI Express* Registers (D1:F0)
6.1.35
DCAP—Device Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
A4–A7h
00008000h
RO
Size:
32 bits
This register indicates PCI Express device capabilities.
Bit
31:16
15
Access &
Default
Description
RO
0000h
Reserved: Not Applicable or Implemented. Hardwired to 0.
RO
1b
Role Based Error Reporting (RBER): This bit indicates that this
device implements the functionality defined in the Error Reporting ECN
as required by the PCI Express 1.1 specification.
14:6
5
RO
000h
Reserved: Not Applicable or Implemented. Hardwired to 0.
RO
0b
Extended Tag Field Supported (ETFS): Hardwired to indicate
support for 5-bit Tags as a Requestor.
4:3
2:0
RO
00b
Phantom Functions Supported (PFS): Not Applicable or
Implemented. Hardwired to 0.
RO
Max Payload Size (MPS): Hardwired to indicate 128B max supported
000b
payload for Transaction Layer Packets (TLP).
Datasheet
189
INTEL [ INTEL ]
