PCI Express* Registers (D1:F0)
6.1.36
DCTL—Device Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
A8–A9h
0000h
RO, RW
16 bits
Size:
This register provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
Bit
15:8
7:5
Access &
Default
Description
RO
000h
Reserved
RW
Max Payload Size (MPS):
000b
000 = 128B max supported payload for Transaction Layer Packets
(TLP). As a receiver, the Device must handle TLPs as large as
the set value; as transmitter, the Device must not generate
TLPs exceeding the set value.
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to support
compliance testing.
4
3
RO
0b
Reserved: For Enable Relaxed Ordering
RW
0b
Unsupported Request Reporting Enable (URRE): When set,
allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_CORR to the
Root Control register when detecting an unmasked Unsupported
Request (UR). An ERR_CORR is signaled when an unmasked Advisory
Non-Fatal UR is received. An ERR_FATAL or ERR_NONFATAL is sent to
the Root Control register when an uncorrectable non-Advisory UR is
received with the severity bit set in the Uncorrectable Error Severity
register.
2
1
0
RW
0b
Fatal Error Reporting Enable (FERE): When set, enables signaling
of ERR_FATAL to the Root Control register due to internally detected
errors or error messages received across the link. Other bits also
control the full scope of related error reporting.
RW
0b
Non-Fatal Error Reporting Enable (NERE): When set, enables
signaling of ERR_NONFATAL to the Root Control register due to
internally detected errors or error messages received across the link.
Other bits also control the full scope of related error reporting.
RW
0b
Correctable Error Reporting Enable (CERE): When set, enables
signaling of ERR_CORR to the Root Control register due to internally
detected errors or error messages received across the link. Other bits
also control the full scope of related error reporting.
190
Datasheet
INTEL [ INTEL ]
