PCI Express* Registers (D1:F0)
6.1.37
DSTS—Device Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
AA–ABh
0000h
RO, RWC
16 bits
Size:
This register reflects status corresponding to controls in the Device Control register.
The error reporting bits are in reference to errors detected by this device, not errors
messages received across the link.
Bit
15:6
5
Access &
Default
Description
RO
000h
Reserved and Zero: For future R/WC/S implementations; software
must use 0 for writes to bits.
RO
0b
Transactions Pending (TP):
0 = All pending transactions (including completions for any outstanding
non-posted requests on any used virtual channel) have been
completed.
1 = Device has transaction(s) pending (including completions for any
outstanding non-posted requests for all used Traffic Classes).
4
3
RO
0b
Reserved
RWC
0b
Unsupported Request Detected (URD):
0 = Unsupported request Not detected.
1 = Device received an Unsupported Request. Errors are logged in this
register regardless of whether error reporting is enabled or not in
the Device Control Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal Error
Detected bit is set according to the setting of the Unsupported Request
Error Severity bit. In production systems setting the Fatal Error
Detected bit is not an option as support for AER will not be reported.
2
RWC
0b
Fatal Error Detected (FED):
0 = Fatal error Not detected.
1 = Fatal error(s) were detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the
Device Control register.
When Advanced Error Handling is enabled, errors are logged in this
register regardless of the settings of the uncorrectable error mask
register.
Datasheet
191
INTEL [ INTEL ]
