PCI Express* Registers (D1:F0)
6.1.21
CAPPTR1—Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
34h
88h
RO
8 bits
Size:
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
Bit
Access &
Default
Description
7:0
First Capability (CAPPTR1): The first capability in the list is the
Subsystem ID and Subsystem Vendor ID Capability.
RO
88h
6.1.22
INTRLINE1—Interrupt Line
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
3Ch
00h
RW
Size:
8 bits
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
Bit
Access &
Default
Description
7:0
Interrupt Connection (INTCON): Used to communicate interrupt
line routing information.
RW
00h
6.1.23
INTRPIN1—Interrupt Pin
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
3Dh
01h
RO
Size:
8 bits
This register specifies which interrupt pin this device uses.
Bit
Access &
Default
Description
7:0
Interrupt Pin (INTPIN): As a single function device, the PCI Express
device specifies INTA as its interrupt pin. 01h=INTA.
RO
01h
180
Datasheet
INTEL [ INTEL ]
