PCI Express* Registers (D1:F0)
6.1.18
PMLIMIT1—Prefetchable Memory Limit Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
26–27h
0001h
RW, RO
16 bits
Size:
This register in conjunction with the corresponding Upper Limit Address register
controls the processor-to-PCI Express prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register
are read/write and correspond to address bits A[39:32] of the 40-bit address. This
register must be initialized by the configuration software. For the purpose of address
decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined
memory address range will be at the top of a 1MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration
software between the memory ranges that must be defined as UC and the ones that
can be designated as a USWC (i.e. prefetchable) from the processor perspective.
Bit
Access &
Default
Description
15:4
RW
000h
Prefetchable Memory Address Limit (PMLIMIT): This field
corresponds to A[31:20] of the upper limit of the address range passed
to PCI Express.
3:0
RO
1h
64-bit Address Support: This field indicates that the upper 32 bits of
the prefetchable memory region limit address are contained in the
Prefetchable Memory Base Limit Address register at 2Ch
Datasheet
177
INTEL [ INTEL ]
