PCI Express* Registers (D1:F0)
6.1.25
PM_CAPID1—Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/1/0/PCI
80–83h
C8039001h
RO
Size:
32 bits
Bit
Access &
Default
Description
31:27
RO
19h
PME Support (PMES): This field indicates the power states in which
this device may indicate PME wake via PCI Express messaging. D0,
D3hot & D3cold. This device is not required to do anything to support
D3hot & D3cold, it simply must report that those states are
supported. Refer to the PCI Power Management 1.1 specification for
encoding explanation and other power management details.
26
25
RO
0b
D2 Power State Support (D2PSS): Hardwired to 0 to indicate that
the D2 power management state is NOT supported.
RO
0b
D1 Power State Support (D1PSS): Hardwired to 0 to indicate that
the D1 power management state is NOT supported.
24:22
21
RO
000b
Auxiliary Current (AUXC): Hardwired to 0 to indicate that there are
no 3.3Vaux auxiliary current requirements.
RO
0b
Device Specific Initialization (DSI): Hardwired to 0 to indicate
that special initialization of this device is NOT required before generic
class device driver is to use it.
20
19
RO
0b
Auxiliary Power Source (APS): Hardwired to 0.
RO
0b
PME Clock (PMECLK): Hardwired to 0 to indicate this device does
NOT support PME# generation.
18:16
RO
011b
PCI PM CAP Version (PCIPMCV): A value of 011b indicates that this
function complies with revision 1.2 of the PCI Power Management
Interface Specification.
15:8
7:0
RO
90h
Pointer to Next Capability (PNC): This contains a pointer to the
next item in the capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then
the next item in the capabilities list is the Message Signaled
Interrupts (MSI) capability at 90h.
RO
Capability ID (CID): Value of 01h identifies this linked list item
01h
(capability structure) as being for PCI Power Management registers.
Datasheet
183
INTEL [ INTEL ]
